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    • 专利摘要:
    A method of producing a semiconductor device (100), comprising: a) etching a stack of a layer of a second crystalline semiconductor disposed between a substrate (104) and a layer of a first semiconductor crystalline driver, the second semiconductor being different from the first semiconductor and subjected to a compressive stress, forming a stack of nanowires, b) producing a dummy gate and external spacers (112), covering a part the stack of nanowires formed of portions (114) of the nanowires, c) etching of the stack of nanowires such that only said portion of the stack is preserved, d) deleting the portion of the nanowire of the second semiconductor, e) depositing, in a space formed by this deletion, a portion of sacrificial material, f) producing source and drain regions (118, 120) and internal spacers (142), g) deleting the dummy gate and the portion of sacrificial material, h) performing a grid (128).
    公开号:FR3060838A1
    申请号:FR1662529
    申请日:2016-12-15
    公开日:2018-06-22
    发明作者:Shay REBOH；Emmanuel Augendre；Remi COQUAND；Nicolas Loubet
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；International Business Machines Corp；
    IPC主号:
    专利说明:

    Holder (s): COMMISSIONER FOR ATOMIC ENERGY AND ALTERNATIVE ENERGIES Public establishment, INTERNATIONAL BUSINESS MACHINES CORPORATION.
    Extension request (s)
    Agent (s): BREVALEX Limited liability company.
    PROCESS FOR PRODUCING A COMPRESSION DEVICE.
    SEMICONDUCTOR WITH CONSTRAINED CHANNEL
    FR 3 060 838 - A1
    13/1 Method for producing a semiconductor device (100), comprising:
    a) etching a stack of a layer of a second crystalline semiconductor disposed between a substrate (104) and a layer of a first crystalline semiconductor, the second semiconductor being different from the first semiconductor and subjected compressive stress, forming a stack of nanowires,
    b) production of a dummy grid and external spacers (112), covering part of the stack of nanowires formed of portions (114) of the nanowires,
    c) etching of the stack of nanowires such that only said part of the stack is preserved,
    d) removal of the portion of the second semiconductor nanowire,
    e) depositing, in a space formed by this removal, of a portion of sacrificial material,
    f) making source and drain regions (118, 120) and internal spacers (142),
    g) removal of the dummy grid and of the portion of sacrificial material,
    h) production of a grid (128).

    i
    METHOD FOR PRODUCING A CONSTRAINED CHANNEL SEMICONDUCTOR DEVICE
    IN COMPRESSION
    DESCRIPTION
    TECHNICAL AREA AND PRIOR ART
    The invention relates to a method for producing a semiconductor device, such as a GAA-FET transistor (“Gate-AII-Around Field Effect Transistor”, or field effect transistor with a covering grid), with a channel constrained in compression. . The invention also relates to a method for producing N and P type transistors co-integrated on the same substrate and comprising channels constrained differently from one another, that is to say constrained in voltage for the N-type transistor and constrained in compression for the P-type transistor.
    In a GAA-FET type transistor, the gate of the transistor is formed all around the channel such that the channel is surrounded or coated by the gate. The advantage of such a transistor, compared to a conventional MOSFET, is to improve the electrostatic control of the channel by the gate (which makes it possible to reduce the leakage currents of the transistor), in particular when the transistor is completely deserted (for example FD-SOI type, or "Fully-Depleted Silicon On Insulator).
    It is known to produce a GAA-FET type transistor comprising a stack of several semiconductor nanowires together forming the transistor channel. This configuration makes it possible to obtain a good compromise between the electrostatic control of the channel by the gate and the control current required in the transistor.
    Adding a constraint in the transistor channel contributes to improving the performance of the transistor. This constraint is preferably uniaxial and parallel to the direction of movement of the charge carriers in the channel. A compression stress to which the channel is subjected makes it possible to improve the mobility of the charge carriers in a P-type transistor, while a voltage stress has a beneficial effect in a N-type transistor.
    It is for example known to produce a GAA-FET transistor from an alternating stack of layers of silicon and SiGe. The silicon layers are intended to form the nanowires corresponding to the transistor channel. The first layer of the stack comprises SiGe and is placed on a silicon substrate (bulk or SOI). This SiGe, produced by epitaxy from silicon, is constrained in compression in a bi-axial manner due to the difference in lattice parameters between these two materials. On the other hand, the silicon is relaxed and is in an unstressed state.
    This stack is first etched to form nanowires, also called nanosheets, part of which is intended to form the transistor channel. This etching results in an at least partial relaxation of the stress in the SiGe nanowires, at least parallel to the width of these nanowires (this relaxation can also be bi-axial, that is to say parallel to the length and to the width of the nanowires). This relaxation generates a deformation, or stress, in tension in the silicon layers, in the direction parallel to the width of the nanowires, creating a slight stress in tension according to the direction of charge transport in the silicon nanowires.
    After having formed a sacrificial grid and external spacers, the stack of nanowires of silicon and SiGe is etched in order to keep only portions of these nanowires which are covered by the sacrificial grid and the external spacers. Ends of the portions of SiGe covered by the external spacers are etched and the cavities formed by this etching are filled with a dielectric material to form the internal spacers. At this stage of the process, the silicon channels are subjected to a high voltage stress, of increasing intensity from the ends of the channel to its center, generated by the etching of the nanowires.
    The source and drain regions are then formed by epitaxy, then encapsulated.
    The sacrificial grid is then removed and the remaining portions of SiGe disposed between the silicon portions are removed in order to release the portions of silicon nanowires forming the transistor channel. The silicon portions partially relax but retain a tension stress, for example of the order of 0.3 GPa at the center of the channel.
    This voltage stress is beneficial for N-type transistors but is problematic for P-type transistors for which a compression stress of the channel is sought.
    STATEMENT OF THE INVENTION
    An object of the present invention is to propose a production method making it possible, from a stack of initial material favorable to the production of transistors with voltage-constrained channels as described above, to produce a semiconductor device comprising a channel constrained in compression.
    For this, a method of producing a semiconductor device is proposed, comprising at least the following steps:
    a) etching of a stack of layers disposed on a substrate and comprising at least one layer of a second crystalline semiconductor disposed between the substrate and at least one layer of a first crystalline semiconductor and such as the second semi -conductor is different from the first semiconductor and subjected to a compressive stress, forming at least one stack of nanowires comprising at least one nanowire of second semiconductor arranged between the substrate and at least one nanowire of first semiconductor,
    b) production of at least one dummy grid and external spacers between which the dummy grid is disposed, covering at least part of the stack of nanowires formed by portions of the nanowires of the first and second semiconductors,
    c) etching the nanowire stack such that only said part of the nanowire stack is preserved,
    d) removal of the portion of the second semiconductor nanowire,
    e) depositing, in at least one space formed by the removal of the portion of the second semiconductor nanowire, of at least one portion of sacrificial material,
    f) production of source and drain regions and internal spacers around parts of the portion of first semiconductor nanowire covered by the external spacers,
    g) removal of the dummy grid and of the portion of sacrificial material,
    h) production of a grid between the external spacers and around the portion of the first semiconductor nanowire forming a channel.
    In this method, the etchings used in steps a) and c) create a significant uni-axial voltage stress in the portion of the nanowire of first semiconductor obtained at the end of step c), due to the compressive stress in the layer of the second semiconductor of the initial stack. This is particularly well suited for the production of voltage-constrained channels. However, thanks to the elimination of the portion of the nanowire of second semiconductor carried out subsequently, the portion of the nanowire of first semiconductor is no longer subjected to this tension stress generated by the remaining portion of the second nanowire and relaxes for end up in a substantially unstressed state. After the portion of sacrificial material has been deposited in the space formed by the removal of the portion of the second semiconductor nanowire, steps f) to h) complete the production of the semiconductor device without impacting the stress in the portion of the first semiconductor nanowire intended to form the channel of the semiconductor device.
    The uni-axial tension stress created in the portion of the first semiconductor nanowire is parallel to the length (largest dimension) of the first semiconductor nanowire (and parallel to the direction of movement of the charge carriers in the channel intended to be formed by the portion of the first semiconductor nanowire).
    In the initial stack of layers, the second semiconductor is subjected to a compressive stress in a plane parallel to the surface of the substrate on which the stack of layers is arranged.
    When the substrate also comprises a crystalline semiconductor, the compressive stress to which the second semiconductor is subjected in the stack of layers may be due to the larger mesh parameter of the second semiconductor compared to that of the semi -conductor of the substrate.
    The first semiconductor can be similar to that of the substrate. More generally, the lattice parameter of the first semiconductor can be similar to that of the crystalline semiconductor of the substrate.
    In addition, in the initial stack of layers, the second semiconductor may be subjected to a bi-axial compression stress, that is to say constrained by forces oriented in directions lying in the plane of the layer of second semiconductor and perpendicular to each other.
    The term “nanowire” designates any portion of material of nanometric dimensions and of elongated shape, whatever the shape of the section of this portion. Thus, this term designates as many portions of elongated material of circular or substantially circular section, but also portions of material in the form of nano-beams or nano-bars comprising for example a rectangular or substantially rectangular section.
    The internal and external spacers correspond to the dielectric elements electrically insulating the gate from the source and drain regions of the semiconductor device. The internal spacers are arranged in areas adjacent to the junctions, at least under the portion of the nanowire of the first semiconductor. The external spacers cover at least a portion of the source and drain extension regions.
    Advantageously:
    the first semiconductor can be crystalline silicon, and / or
    the second semiconductor may be SiGe having a proportion of germanium greater than about 50%, and / or
    - The portion of sacrificial material can comprise at least one dielectric and / or an amorphous semiconductor (for example rich in hydrogen).
    For example, the portion of sacrificial material may comprise S1O2 and / or amorphous SiGe and / or amorphous germanium and / or amorphous silicon and / or SiN.
    The portion of sacrificial material may comprise an unstressed or tensioned material. An unconstrained material corresponds to a material which is not subjected to a compressive or tensile stress. Such an unconstrained or tension-constrained sacrificial material is well suited to obtaining zero or compression stress in the channel of the device. A sacrificial material constrained in tension generates a compressive stress in the channel as soon as it is deposited when this stress is intrinsic to the material. If the stress in tension is generated in the sacrificial material after its deposition, for example during a thermal annealing or a recrystallization, the compressive stress is generated in the channel during this annealing or this recrystallization.
    The compression stress in the channel can be generated by depositing amorphous silicon or amorphous SiGe, rich in hydrogen, and then recrystallizing it. This constraint is in this case generated by the contraction, or reduction in volume, of the sacrificial material, during the passage from the amorphous state to the crystalline state. Before the deposition of amorphous silicon or amorphous SiGe, an oxide layer can be formed at least around the channels to then allow selective removal of the sacrificial material.
    When the sacrificial material generates a compressive stress in the channel, this stress is transferred to the source and drain regions which are produced by epitaxy from the semiconductor of the channel. Thus, this compressive stress remains in the source and drain regions even after the subsequent removal of the sacrificial material.
    The second semiconductor layer may preferably have a thickness less than its critical plastic relaxation thickness. Thus, the appearance of defects in the channel which would be caused by plastic relaxation of the material of the second semiconductor layer during the process is avoided. When the second semiconductor is SiGe, the value of this critical plastic relaxation thickness depends notably on the germanium concentration in the SiGe.
    Step f) may include the implementation of:
    - etching of parts of the portion of sacrificial material covered by the external spacers, then
    - Realization of internal spacers in cavities formed by the removal of said parts of the portion of sacrificial material, then
    - creation of source and drain regions.
    According to a particular embodiment, the method can also comprise, between steps g) and h), the implementation of the following steps:
    - thinning of the portion of the first semiconductor nanowire,
    - epitaxy of a layer of a third semiconductor constrained in compression around the portion of the nanowire of first semiconductor, preferably in a conforming manner.
    By carrying out such an epitaxy, the compressive stress in the third epitaxial semiconductor, due for example to the difference in lattice parameters between the first semiconductor and the third semiconductor, is then found in the nanowire portion of first semiconductor which is intended to form the channel of the semiconductor device, which improves the performance of the semiconductor device.
    In this case, the method can also comprise, after the epitaxy of the layer of third semiconductor and before step h), the implementation of an annealing effecting a diffusion of atoms of the third semiconductor at least in the portion of the first semiconductor nanowire.
    According to another particular embodiment, the method can also comprise, between steps g) and h), the implementation of the following steps:
    - epitaxy of a layer of a third semiconductor constrained in compression around the portion of the nanowire of first semiconductor,
    annealing producing a diffusion of atoms of the third semiconductor at least in the portion of the nanowire of first semiconductor,
    - Thinning of the assembly comprising the layer of third semiconductor and the portion of the nanowire of first semiconductor.
    The thinning and epitaxy steps can be implemented such that, at the end of these steps, the thickness of the assembly comprising the layer of third semiconductor and the portion of the nanowire of first semiconductor is substantially equal to the thickness of the portion of the nanowire of first semiconductor before the implementation of these steps. This characteristic is advantageously obtained when the thinning is carried out before the epitaxy because the thickness of the epitaxial semiconductor is more easily controllable than the thickness of the semiconductor removed during the thinning.
    The production of the source and drain regions may include the implementation of at least one epitaxy of SiGe having a proportion of germanium of between approximately 20% and 80%, forming the source and drain regions.
    Advantageously, the production of the source and drain regions can comprise at least the implementation of a first epitaxy from at least the portion of the nanowire of the first semiconductor, forming a first part of the source and drain regions , then a second epitaxy from the first part of the source and drain regions, forming a second part of the source and drain regions.
    In this case, the first epitaxy can be implemented such that the first part of the source and drain regions comprises semiconductor including carbon atoms. The fact of carrying out the first part of the source and drain regions by including carbon atoms makes it possible to avoid or reduce an uncontrolled diffusion of the dopants present in the source and drain regions from these regions into the channel during the epitaxy of the second part of the source and drain regions.
    The stack of layers may comprise several layers of first semiconductor and several layers of second semiconductor stacked alternately on top of each other, the stack of nanowires obtained at the end of step a) comprising several second semiconductor nanowires and multiple first semiconductor nanowires.
    Advantageously, the semiconductor device can be a P-type GAA-FET transistor. Thus, this method makes it possible to produce a P-type transistor from a stack of layers suitable for producing a type-transistor. NOT.
    A method is also proposed for producing N and P type transistors co-integrated on the same substrate, comprising at least the following steps:
    - implementation of steps a) to c) of the method for producing a semiconductor device, such that several remaining parts of the stack of layers each covered by a dummy grid and by external spacers form first and second structures intended to form the N and P type transistors respectively,
    - formation of at least a first encapsulation material on the first structures,
    implementation of steps d) to h) of the method for producing a semiconductor device from the second structures, forming the P-type transistors,
    elimination of the first encapsulation material and formation of at least one second encapsulation material on the P-type transistors,
    - making N-type transistors from the first structures.
    A method is also proposed for producing N and P type transistors co-integrated on the same substrate, comprising at least the following steps:
    - Implementation of steps a) to c) of the method for producing a semiconductor device, such that several remaining parts of the stack of layers each covered by a dummy grid and by external spacers form first and second structures intended to form the N and P type transistors respectively,
    - formation of at least a first encapsulation material on the second structures,
    - making N-type transistors from the first structures,
    - Removal of the first encapsulation material and formation of at least one second encapsulation material on the N type transistors, ίο
    - implementation of steps d) to h) of the method for producing a semiconductor device from the second structures, forming the P-type transistors.
    A method of making N and P type transistors is thus proposed, making it possible to obtain both a voltage stress in the channels of N type transistors (the etchings implemented in steps a) and c) create a constraint. in significant uni-axial tension in the portion of the nanowire of first semiconductor obtained at the end of step c), due to the compressive stress in the layer of the second semiconductor of the initial stack) and a compressive stress in the channels of the P-type transistors, thus giving good performance to all the transistors produced.
    The production of N-type transistors may include at least the following steps:
    - production of source and drain regions and internal spacers around parts of the nanowire portion of the first semiconductor covered by the external spacers,
    - elimination of the dummy grid and of the nanowire portion of the second semiconductor,
    - Creation of a grid between the external spacers and around the portion of the nanowire of the first semiconductor forming a channel.
    BRIEF DESCRIPTION OF THE DRAWINGS
    The present invention will be better understood on reading the description of exemplary embodiments given for purely indicative and in no way limiting, with reference to the appended drawings in which:
    FIGS. IA to IL represent the steps of a method for producing a semiconductor device, object of the present invention, according to a first embodiment,
    FIGS. 2A and 2B represent a part of the steps of a method for producing a semiconductor device, object of the present invention, according to a second embodiment,
    - Figures 3A and 3B show the values of the stress obtained in the active area of a GAA-FET transistor produced according to different methods, including the method according to the invention.
    Identical, similar or equivalent parts of the different figures described below have the same reference numerals so as to facilitate the passage from one figure to another.
    The different parts shown in the figures are not necessarily shown on a uniform scale, to make the figures more readable.
    The different possibilities (variants and embodiments) must be understood as not being mutually exclusive and can be combined with one another.
    DETAILED PRESENTATION OF PARTICULAR EMBODIMENTS
    Reference is made to FIGS. IA to IL which represent the steps implemented for the production of a semiconductor device 100, corresponding here to a P-type GAA-FET transistor, according to a first embodiment.
    The device 100 is produced from a stack of layers of two different crystalline semiconductors placed on a substrate 104. In the first embodiment described here, the substrate 104 corresponds to a solid substrate, or “bulk”, of semiconductor, for example of silicon, on which is placed the stack comprising first and second layers of two different semiconductors arranged alternately one above the other. Each of the first layers is intended to form a semiconductor nanowire of the channel of the device 100 and is arranged between two second layers comprising a material capable of being selectively etched relative to that of the first layers as well as relative to the materials intended to be subsequently used to form a dummy grid and external and internal spacers. In the first embodiment described here, this stack comprises three first layers as well as four second layers arranged in an alternating manner such that each of the first layers is disposed between two second layers.
    The materials of the first and second layers correspond to first and second crystalline semiconductors which can be formed by epitaxy on the substrate 104.
    In the example described here, the substrate 104 and the first layers comprise silicon and the second layers comprise SiGe with a proportion of germanium for example of between approximately 30% (SioyGeoq) and 60% (Sio, 4Geo, 6).
    As a variant, the substrate used can correspond to an SOI substrate (silicon on insulator), with in this case the surface layer, or thin layer, of the SOI substrate which can form one of the second layers of the stack (when the second layers include SiGe, an enrichment of Ge is carried out in the silicon of the surface layer in order to transform this silicon into SiGe).
    Advantageously, the substrate 104 and the first and second layers of the stack are suitable for producing P-type transistors such as the device 100, but also N-type transistors. Thus, in order to impart a high voltage stress in the channels of N-type transistors, the germanium concentration in the SiGe of the second layers is advantageously greater than or equal to approximately 50%, or even greater than or equal to approximately 60%. In other words, the material of the second layers is advantageously SixGei-x with X <0.5 or X <0.4.
    Each of the first and second layers has, for example, a thickness of between about 5 nm and 9 nm. However, the thickness of each of the second layers is chosen such that it is less than its critical thickness of plastic relaxation, in order to avoid a loss of stress and the creation of defects in the channels of the transistors. This critical thickness of plastic relaxation corresponds to the thickness of material beyond which the accumulated elastic energy is sufficient for dislocations to form and depends in particular, in the case of a layer of
    SiGe, germanium concentration of SiGe. Thus, for a layer of SiO, 4Geo, 6 formed on a layer of silicon, the critical thickness of elastic relaxation is equal to approximately 10 nm. Details concerning the determination of this critical thickness of plastic relaxation are given for example in the document "Critical thickness for plastic relaxation of SiGe on Si (001) revisited" by J.M. Hartmann et al., J. Appl. Phys. 110, 083529, 2011.
    The stack of layers comprising the first and second layers is etched in the form of an elongated portion as shown in FIG. IA, and forming a stack 102 of nanowires disposed on the substrate 104. When several devices 100 are produced collectively at from the same stack of layers, several stacks 102 are produced.
    The portions from the first layers form first nanowires 108 of the first semiconductor and the portions from the second layers form second nanowires 106 of the second semiconductor. In the example of FIG. IA, the stack 102 comprises three first nanowires 108 each disposed between two second nanowires 106.
    The width of the stack 102, which corresponds to the dimension along the Y axis, is equal to the desired width of the first nanowires 108 intended for producing the channel of the device 100.
    A dummy grid 110 is then produced, for example by lithography and etching, on the stack 102, at the location intended for the future grid of the device 100. The dummy grid 110 is formed on portions of the first nanowires 108 intended to form the channel of the device 100, and portions of the second nanowires 106 between which these portions of the first nanowires 108 are located, and also covers the lateral flanks of the nanowires 106, 108 of the stack 102.
    External spacers 112 are then produced, for example by deposition and etching, on the stack 102, and against the lateral flanks of the dummy grid 110. These external spacers 112 cover parts of the second nanowires 108 intended to lie on either side and other of the junctions. The length, or depth, of these external spacers 112 (dimension parallel to the axis X represented in FIG. 1A) is for example between approximately 3 and 8 nm. The external spacers 112 are intended to isolate the grid from the source and drain.
    The dummy grid 110 comprises for example amorphous or polycrystalline silicon, and the external spacers 112 comprise for example SiN and / or S13N4 and / or SiBCN.
    The parts of the stack 102 not covered by the dummy grid 110 and by the external spacers 112 are also engraved (FIG. 1B), for example during the engraving of the external spacers 112. The remaining portions 114 of the first nanowires 108 are intended for forming the channel of the device 100. Each of the portions 114 is interposed between two remaining portions 116 of the second nanowires 106. The remaining portions 114 and 116 correspond to nanowires (of shorter length than that of the initial nanowires 106,108).
    The portions 116 of the nanowires of second semiconductor are then selectively etched with respect to the other materials present, that is to say with respect to the first semiconductor of the portions 114 (thanks to the fact that the concentration in germanium in the second semiconductor is greater than that in the first semiconductor), of the dummy gate material 110 and of the material of the external spacers 112, forming cavities 136 between which the portions 114 are located (FIG. IC) .
    A sacrificial material capable of being selectively etched with respect to the portions 114, the dummy grid 110, the external spacers 112, the future source and drain regions of the device 100 and the future internal spacers of the device 100, is then deposited in the cavities 136, forming portions 138 between which the portions 114 are arranged (FIG. 1D). The material of the portions 138 corresponds for example to an amorphous semiconductor such as SiGe with a high germanium concentration (for example greater than or equal to about 20%), or else germanium. For example, when the source and drain regions of the device 100 are intended to be produced subsequently in SiGe, the germanium concentration in the SiGe of the portions 138 can be at least 20% higher than that of the SiGe of the regions source and drain. In this case, the portions 138 can be formed via a selective deposition process such that the material of the portions 138 is deposited only around the portions 114.
    As a variant, the material of the portions 138 can be a dielectric material such as SiN or SiBCN, such a dielectric material cannot be found initially in a stack of crystalline layers formed by epitaxy. In this case, the dielectric material deposited outside the cavities 136 (due to the non-selective deposition which is used to form such portions 138) is removed before the process is continued, for example via the directive implementation such as 'an engraving RIE.
    It is also possible to choose, for the production of the portions 138, a sacrificial material intrinsically comprising a tensile stress and which then generates, in the portions 114, a compressive stress. Such a material corresponds, for example, to amorphous silicon rich in hydrogen or to amorphous SiGe rich in hydrogen, or else to SiN comprising a stress in tension. In the case of portions 138 produced with silicon or SiGe, amorphous and rich in hydrogen, a recrystallization step of these semiconductors is carried out after their deposition to generate a compressive stress in the channel. This stress is generated by the contraction, or reduction in volume, during the crystalline amorphous transformation. Before depositing the Si or SiGe to form the portions 138, an oxide layer is advantageously deposited around the portions 114 so as to be able to subsequently carry out a selective removal of the portions 138.
    The sacrificial material of the portions 138 is therefore here chosen such that it does not correspond to a material constrained in compression. Thus, the sacrificial material of the portions 138 corresponds either to an unconstrained material, or else a material constrained in tension. Thus, having replaced the portions of SiGe 116 by the portions 138 of material not constrained in compression, the silicon of the portions 114, which was strongly stressed in tension due to the presence of the portions of SiGe 116, relaxes and the stress in tension in the silicon portions 114 becomes substantially zero (and possibly replaced by a compressive stress).
    The parts, or ends, of the portions 138 covered by the external spacers 112 are etched, forming cavities 140 between which the ends of the portions 114 are located (FIG. 1E).
    As shown in FIG. 1F, the cavities 140 are filled with dielectric material with low permittivity (less than about 3.9) forming internal spacers 142.
    At this stage of the process, unlike the process of the prior art in which the semiconductor portions intended to form the channel is subjected to a high voltage stress, of increasing intensity from the ends of the channel to its center , the material (silicon) of the remaining portions 114 is unconstrained or subjected to a greatly reduced tension stress thanks to the removal of the SiGe 116 portions, or else subjected to a compression stress.
    As shown in FIG. IG, source and drain regions 118, 120 are then produced by epitaxy on the substrate 104, from the ends of the portions 114 (and of the substrate 104 when it comprises a crystalline semiconductor from which a epitaxy can be performed). These source and drain regions 118, 120 are produced with one or more layers having in situ doping so as to obtain a good quality of junction. For example, the doping of the material of the source and drain regions 118, 120 can be carried out with doping atoms of Boron whose concentration is for example between approximately 10 18 and 10 21 at / cm 3 . The material of the source and drain regions 118, 120 is here SiGe: B.
    In the first embodiment described here, the source and drain regions 118, 120 comprise SiGe. The germanium concentration of SiGe in the source and drain regions 118, 120 is for example between approximately 20% (Sio, 8Geo, 2) θΐ 80%. (SioqGeo.s).
    According to a particular embodiment, it is possible that the source and drain regions 118, 120 are obtained by using several epitaxies, allowing the growth of materials of different compositions (for example by varying the concentration of germanium between the epitaxies) and / or different dopant concentrations. For example, the production of the source and drain regions 118, 120 may comprise the implementation of a first epitaxy of SiGe comprising carbon atoms, then of a second epitaxy of SiGe not comprising carbon atoms . Thus, because the epitaxy is implemented with in situ doping of the source and drain regions 118, 120 formed, the portion of SiGe comprising carbon atoms formed initially makes it possible to reduce the diffusion of dopants in the region of device channel 100.
    When the material of the substrate 104 on which the stack is placed is also a crystalline material, the surface of this material is also used for the growth of the crystalline material of the source and drain regions 118, 120.
    When the material of the portions 114 is subjected to a compressive stress provided by the portions of sacrificial material 138, this compressive stress is then found in the source and drain regions 118, 120.
    An encapsulation material 122 is then deposited on the source and drain regions 118, 120 (FIG. 1H) so as not to alter these regions during the implementation of the subsequent steps.
    As shown in FIG. 11, the dummy grid 110 is then removed, revealing the portions 114 and 138.
    Selective etching of the portions of sacrificial material 138 with respect to the portions 114 of the nanowires of the first semiconductor, of the source and drain regions 118, 120 and of the external spacers 112 is then implemented in order to release the portions 114 intended forming the channel of the device 100. This etching corresponds for example to a chemical etching HCI / H2. This engraving also reveals, in the space freed up between the external spacers 112, the internal spacers 142.
    A grid 128, comprising at least one grid dielectric and a grid conductive material, is then produced between the external spacers 112, at the location previously occupied by the dummy grid 110 (FIG. IK). The grid 128 thus produced surrounds the portions 114 and is electrically isolated from the source and drain regions 118, 120 by the internal spacers 142 and the external spacers 112.
    Thus, the internal spacers 142 make it possible to reduce the capacitive effects between the gate 128 and the source and drain regions 118, 120.
    The device 100 is completed by partially removing the encapsulation material 122, forming accesses to reach the gate, the source and the drain, and by forming electrical contacts 130, 132 and 134 on the source and drain regions 118, 120 and on grid 128 (figure IL).
    The P-type GAA-FET transistor 100 thus obtained comprises a channel formed by the nanowires corresponding to the portions 114 which comprise silicon not stressed in tension or very slightly stressed in tension, or else constrained in compression, by replacing the initial constrained SiGe in compression by the sacrificial material of the portions 138 produced during the process.
    When the sacrificial material of the portions 138 is of the semiconductor, an epitaxy step from this semiconductor can be implemented before the epitaxy forming the source and drain regions 118, 120. In this case, the source and drain regions may comprise a semiconductor different from that previously epitaxied, for example SiGe if amorphous Si is used previously to form the portions 138, or Si or SiGe comprising less Ge than that of the portions 138 when the portions 138 comprise SiGe.
    The embodiment of the P-type GAA-FET transistor 100 according to a second embodiment is now described in connection with FIGS. 2A and 2B.
    The steps previously described in connection with Figures IA to IJ are first implemented. At the end of these steps, the silicon of the remaining portions 114 is relaxed and not stressed. The steps which are then implemented and described below in connection with FIGS. 2A and 2B make it possible to confer a significant compressive stress on the semiconductor of the channel of transistor 100.
    For this, the portions 114 are thinned, for example at least a thickness of between approximately 1 nm and 3 nm per edge, in order to expose portions 124 coming from the portions 114 and being in the regions of extension of the sources. and drain (parts of the first semiconductor surrounded by the external spacers 112) and which are arranged between the internal spacers 142 (FIG. 2A). This thinning can be obtained by implementing an oxidation of the first semiconductor of the portions 114 and then etching of the oxidized semiconductor. These steps can be implemented simultaneously, or during the same set of steps, with the oxidation and etching steps forming the internal spacers 142.
    An epitaxy of a third semiconductor, for example an III-V semiconductor such as SiGe or germanium, is then implemented on the thinned portions 114 (FIG. 2B). The layers 126 formed by this conformal epitaxy (that is to say forming layers of equal thickness on all sides of the portions 114) surround the portions of the portions 114 intended to form the channel. Advantageously, the thickness of the epitaxial layer 126 is substantially equal to the thickness of the semiconductor etched during the previous thinning. Thus, the outer edges of the layer 126 are aligned with the initial interfaces (before thinning) between the internal spacers 142 and the portions 114. The SiGe of the layers 126 epitaxied on the portions 114 has a germanium concentration of between approximately 20% and 100%, and advantageously a germanium concentration of between approximately 20% and 80% when this epitaxy is followed by the implementation of thermal annealing, or approximately 30% and 40% in the absence of this thermal annealing.
    Because the silicon in the portions 114 has been previously relaxed by replacing the portions 116 with the portions of sacrificial material 138, this epitaxy of SiGe around the portions 114 generates a significant compressive stress on the silicon of the portions 114, which allows the production of high performance P-type transistors. At this stage of the process, the channel of transistor 100 is therefore formed by the silicon portions 114 and by the layers of SiGe 126.
    Optionally, a thermal annealing can then be implemented so as to diffuse the third semiconductor of the layers 126 in the silicon of the portions 114 in order to obtain a more homogeneous material, corresponding to SiGe highly constrained in compression and forming the channel of the device 100. This annealing can also modify the semiconductor located in the source and drain extension regions (portions of semiconductor coming from layers 108 and being between the internal spacers 142) due to the migration of germanium can come from layers 126 or else from the source and drain regions 118, 120, making it possible to obtain a more homogeneous material also in the source and drain extension regions. The parameters for implementing the annealing are also chosen such that the migration of the dopants from the source and drain to the channel is limited as much as possible.
    The method is then completed as previously described for the first embodiment, that is to say by implementing the steps previously described in connection with FIGS. 1K and IL.
    The use of a sacrificial material constrained in compression for the production of the portions 138 which has been previously described in connection with the first embodiment can also apply for this second embodiment.
    A third embodiment of the P-type GAA-FET transistor 100 is now described.
    The steps previously described in connection with Figures IA to IJ are first implemented. At the end of these steps, the silicon of the portions 114 is unstressed in voltage. As in the second embodiment, the steps which are then implemented and described below make it possible to confer a significant compressive stress on the semiconductor of the channel of transistor 100.
    Unlike the second embodiment in which the remaining portions 114 are thinned before carrying out an epitaxy on the thinned portions 114, the method according to the third embodiment firstly comprises the implementation of an epitaxy of a third semi -conductor, such as SiGe, on the portions 114. The layers of the third epitaxial semiconductor surround each portion 114. The epitaxial SiGe has a germanium concentration of between approximately 20% and 100% (that is to say corresponds to germanium in the case of a concentration equal to 100%). The epitaxial SiGe can be amorphous. The thickness of the epitaxied SiGe layers is preferably less than approximately half the distance separating two neighboring portions 114.
    A thermal annealing is then implemented in order to diffuse the germanium from the epitaxial layers of SiGe towards the silicon of the portions 114. As in the second embodiment, this annealing can also modify the semiconductor being in the regions of extension of source and drain (portions of semiconductor coming from the layers of the first semiconductor and lying between the internal spacers 142) due to the migration of germanium which can come from the epitaxial layers of SiGe or else from the source and drain regions 118, 120, making it possible to obtain a more homogeneous material also in the source and drain extension regions.
    A thinning of the assembly formed by the annealing of the portions 114 and of the layers 126 is then carried out in order to obtain nanowires having the desired thickness. This thinning can be obtained by implementing an oxidation of the semiconductor of this assembly, then an etching of the oxidized semiconductor.
    Advantageously, the thickness of the nanowires after thinning is substantially equal to the initial thickness of the portions 114.
    The process is then completed as described above for the second embodiment.
    The use of a sacrificial material constrained in compression for the production of the portions 138 which was previously described in connection with the first embodiment can also apply for this third embodiment.
    The curve 10 visible in FIG. 3A represents the stress within the different regions (the part referenced 50 corresponds to the source, that referenced 52 corresponds to the extension region lying between the source and the channel, that referenced 54 corresponds to the channel, that referenced 56 corresponds to the extension region located between the drain and the channel, and that referenced 58 corresponds to the drain) of a GAA-FET transistor produced with a process similar to the second embodiment described above, in which a thermal annealing is implemented in order to diffuse the germanium from the layers 126 in the portions 114 of silicon, but in which the portions of SiGe 116 are not replaced by the portions 138 of sacrificial material (steps of FIGS. IC and 1D not implemented). By way of comparison, the curve referenced 12 represents the stress within the different regions of the GAA-FET transistor produced with a method according to the second embodiment, in which thermal annealing is carried out in order to diffuse the germanium from the layers 126 in the portions 114 and in which the portions of SiGe 116 are indeed replaced by the portions of sacrificial material 138. It is clearly visible in FIG. 3A that the replacement of the portions of SiGe 116 by the portions of sacrificial material 138 makes it possible to increase the compressive stress in the active area of transistor 100, and in particular in the channel.
    Similarly, the curve 14 visible in FIG. 3B represents the stress within the different regions of a GAA-FET transistor produced with a process similar to the second embodiment described above, but in which no thermal annealing is applied. implemented in order to diffuse the germanium from the layers 126 into the remaining portions 114 of silicon, and in which the portions of SiGe 116 are not replaced by the portions 138 of sacrificial material. The curve referenced 16 represents the stress within the different regions of the GAAFET transistor produced with a method according to the second embodiment, in which no thermal annealing is implemented in order to diffuse the germanium from the layers 126 in the portions 114 but in which the portions of SiGe 116 are well replaced by the portions of sacrificial material 138. Here again, it is clearly visible in FIG. 3B that the replacement of the portions of SiGe 116 makes it possible to increase the compressive stress in the active area of the transistor 100, and in particular in the channel.
    The curves 10 - 16 of FIGS. 3A and 3B show that the replacement of the portions of SiGe 116 by the portions 138 of sacrificial material allow, whether or not thermal annealing is used to diffuse germanium in the silicon nanowires, d '' obtain an increase in compressive stress in the transistor channel of the order of 50%.
    The values represented in FIGS. 3A and 3B apply to specific embodiments and may change depending on the characteristics of the transistors: dimensions, materials, etc.
    In the various embodiments described above, the GAA-FET 100 transistor of the P type is produced from a stack of layers favorable to the production of N type transistors due to the large voltage stress present in the portions of silicon 114 at the end of the steps described in connection with Figures IA and IB.
    We will now describe the implementation of a process for the collective production of N and P type transistors co-integrated on the same substrate and produced from the same stack of layers.
    The steps previously described in connection with steps IA and IB are therefore implemented collectively for all of the N and P type transistors intended to be produced.
    Then, the structures obtained intended to form the N-type transistors are protected by depositing one or more encapsulation materials on these structures, and the steps previously described in connection with FIGS. IC to IL (and possibly the additional steps specific to the second or third embodiment) are then implemented to produce the P-type transistors.
    The encapsulation materials previously formed to protect the structures intended for producing the N-type transistors are then removed, and one or more encapsulation materials are then formed on the P-type transistors. The N-type transistors are then produced via the implementation of analogous steps (the dopings are adapted to correspond to those of the N type transistors) to those previously described in connection with FIGS. 1E to IL.
    As a variant, after having implemented the steps described in connection with FIGS. IA and IB, it is possible to make the N type transistors before those of the P type, that is to say to deposit one or more materials of encapsulation protecting the structures intended to form the P-type transistors, then implementing the steps previously described in connection with FIGS. 1E to IL to form the N-type transistors, then removing the encapsulation material (s) protecting the structures intended to form the P-type transistors, then to protect the N-type transistors, and finally to complete the realization of the P-type transistors via the implementation of the steps of Figures IC to IL and possibly additional steps of one of the second and third embodiments.
    权利要求:
    Claims (17)
    [1" id="c-fr-0001]
    1. Method for producing a semiconductor device (100), comprising at least the following steps:
    a) etching a stack of layers disposed on a substrate (104) and comprising at least one layer of a second crystalline semiconductor disposed between the substrate and at least one layer of a first crystalline semiconductor and such that the second semiconductor is different from the first semiconductor and subjected to a compressive stress, forming at least one stack (102) of nanowires comprising at least one nanowire of second semiconductor (106) disposed between the substrate and at least a first semiconductor nanowire (108),
    b) making at least one dummy grid (110) and external spacers (112) between which the dummy grid is disposed, covering at least part of the stack of nanowires formed by portions (114, 116) of the nanowires first and second semiconductors,
    c) etching the nanowire stack such that only said part of the nanowire stack is preserved,
    d) removal of the portion of the second semiconductor nanowire,
    e) depositing, in at least one space (136) formed by the removal of the portion of the second semiconductor nanowire, of at least one portion of sacrificial material (138),
    f) making source and drain regions (118, 120) and internal spacers (142) around parts of the nanowire portion of the first semiconductor covered by the external spacers,
    g) removal of the dummy grid and of the portion of sacrificial material,
    h) production of a grid (128) between the external spacers and around the portion of the first semiconductor nanowire forming a channel.
    [2" id="c-fr-0002]
    2. Method according to claim 1, in which:
    the first semiconductor is silicon, and / or
    the second semiconductor is SiGe having a proportion of germanium greater than about 50%, and / or
    - The portion of sacrificial material (138) comprises at least one dielectric and / or an amorphous semiconductor.
    [3" id="c-fr-0003]
    3. Method according to one of the preceding claims, wherein the portion of sacrificial material (138) comprises an unstressed or tensioned material.
    [4" id="c-fr-0004]
    4. Method according to one of the preceding claims, wherein the second semiconductor layer has a thickness less than its critical plastic relaxation thickness.
    [5" id="c-fr-0005]
    5. Method according to one of the preceding claims, in which step f) comprises the implementation of:
    - etching of parts of the portion of sacrificial material (138) covered by the external spacers (112), then
    - Production of internal spacers (142) in cavities (140) formed by the removal of said parts of the portion of sacrificial material (138), then
    - creation of the source and drain regions (118,120).
    [6" id="c-fr-0006]
    6. Method according to one of the preceding claims, further comprising, between steps g) and h), the implementation of the following steps:
    - thinning of the portion (114) of the nanowire of the first semiconductor,
    - Epitaxy of a layer (126) of a third semiconductor constrained in compression around the portion (114) of the nanowire of first semiconductor.
    [7" id="c-fr-0007]
    7. The method of claim 6, further comprising, after the epitaxy of the third semiconductor layer (126) and before step h), the implementation of an annealing effecting a diffusion of atoms of the at least third semiconductor in the portion (114) of the first semiconductor nanowire.
    [8" id="c-fr-0008]
    8. Method according to one of claims 1 to 5, further comprising, between steps g) and h), the implementation of the following steps:
    - epitaxy of a layer (126) of a third semiconductor constrained in compression around the portion (114) of the nanowire of first semiconductor,
    - annealing producing a diffusion of atoms of the third semiconductor at least in the portion (114) of the nanowire of first semiconductor,
    - Thinning of the assembly comprising the layer (126) of third semiconductor and the portion (114) of the nanowire of first semiconductor.
    [9" id="c-fr-0009]
    9. Method according to one of claims 6 to 8, in which the thinning and epitaxy steps are implemented such that at the end of these steps, the thickness of the assembly comprising the layer ( 126) of the third semiconductor and the portion (114) of the nanowire of first semiconductor is substantially equal to the thickness of the portion (114) of the nanowire of first semiconductor before the implementation of these steps.
    [10" id="c-fr-0010]
    10. Method according to one of the preceding claims, in which the production of the source and drain regions (118, 120) comprises the use of at least one epitaxy of SiGe having a proportion of germanium of between approximately 20% and 80%, forming the source and drain regions (118,120).
    [11" id="c-fr-0011]
    11. Method according to one of the preceding claims, in which the production of the source and drain regions (118, 120) comprises at least the implementation of a first epitaxy from at least the portion (114) of the nanowire. first semiconductor, forming a first part of the source and drain regions (118, 120), then a second epitaxy from the first part of the source and drain regions (118, 120), forming a second part of the regions of source and drain (118, 120).
    [12" id="c-fr-0012]
    12. The method of claim 11, wherein the first epitaxy is implemented such that the first part of the source and drain regions (118, 120) comprises semiconductor including carbon atoms.
    [13" id="c-fr-0013]
    13. Method according to one of the preceding claims, in which the stack of layers comprises several layers of first semiconductor and several layers of second semiconductor stacked alternately on one another, the stack (102) of nanowires obtained at the end of step a) comprising several nanowires of second semiconductor (106) and several nanowires of first semiconductor (108).
    [14" id="c-fr-0014]
    14. Method according to one of the preceding claims, in which the semiconductor device (100) is a P-type GAA-FET transistor.
    [15" id="c-fr-0015]
    15. Method for producing N and P type transistors (100) co-integrated on the same substrate (104), comprising at least the following steps:
    - Implementation of steps a) to c) of a method according to one of the preceding claims, such as several remaining parts of the stack of layers each covered by a dummy grid (110) and by external spacers (112 ) form first and second structures intended to form the N and P type transistors respectively,
    - formation of at least a first encapsulation material on the first structures,
    - implementation of steps d) to h) of the method according to one of the preceding claims from the second structures, forming the P-type transistors,
    elimination of the first encapsulation material and formation of at least one second encapsulation material on the P-type transistors,
    - making N-type transistors from the first structures.
    [16" id="c-fr-0016]
    16. Method for producing N and P type transistors (100) co-integrated on the same substrate (104), comprising at least the following steps:
    - Implementation of steps a) to c) of a method according to one of claims 1 to 14, such as several remaining parts of the stack of layers each covered by a dummy grid (110) and by external spacers (112) form first and second structures intended to respectively form the N and P type transistors,
    - formation of at least a first encapsulation material on the second structures,
    - making N-type transistors from the first structures,
    elimination of the first encapsulation material and formation of at least one second encapsulation material on the N-type transistors,
    - Implementation of steps d) to h) of the method according to one of claims 1 to 14 from the second structures, forming the P-type transistors.
    [17" id="c-fr-0017]
    17. Method according to one of claims 15 and 16, in which the production of the N-type transistors comprises at least the following steps:
    - making source and drain regions (118, 120) and internal spacers (142) around parts of the portion (114) of nanowire of the first semiconductor covered by the external spacers (112),
    - removal of the dummy grid (110) and of the portion (116) of the second semiconductor nanowire,
    - Producing a grid (128) between the external spacers (112) and around the portion (114) of the nanowire of the first semiconductor forming a channel.
    S.60907
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    法律状态:
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    2018-06-22| PLSC| Publication of the preliminary search report|Effective date: 20180622 |
    2019-12-31| PLFP| Fee payment|Year of fee payment: 4 |
    2020-12-28| PLFP| Fee payment|Year of fee payment: 5 |
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    优先权:
    申请号 | 申请日 | 专利标题
    FR1662529A|FR3060838B1|2016-12-15|2016-12-15|METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE WITH A COMPRESSION-CONSTANT CHANNEL|
    FR1662529|2016-12-15|FR1662529A| FR3060838B1|2016-12-15|2016-12-15|METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE WITH A COMPRESSION-CONSTANT CHANNEL|
    US15/837,281| US10431683B2|2016-12-15|2017-12-11|Method for making a semiconductor device with a compressive stressed channel|
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